International Conference Publications

2008

R. R Rydberg, J. Nyathi, J. Delgado-Firas, "Clock skew tolerant communication scheme for SoC IP blocks," 51st IEEE International MidWest Symposium on Circuits and Systems, Knoxville, Tennessee, USA, August 10-13, 2008, pp. 358-361.

2007

J. Nyathi, S. Sankar and P. P. Pande, “Multiple Clock Domain Synchronization for Network on Chip Architectures,” IEEE    International System on a Chip Conference (SoCC), Hsinchu, Taiwan, September 27-29, 2007, pp. 29-294.
H. J. Lin, J. Nyathi and C. Cole, “Evaluation of CPU Utilization Under a Hardware-Software Partitioned Environment (Migrating Software to Hardware),” The 2007 International conference on Embedded Systems and Applications (ESA’07), Las Vegas, Nevada, June 25-28, 2007 pp 222-228.

2006

J. Nyathi and B. Bero, “Logic Circuits Operating in Subthreshold Voltages,” International Symposium on Low Power Electronic Design (ISLPED), 2006, Tergensee, Germany, October 4-6, 2006, pp. 131-134.
B. Bero and J. Nyathi, “Bulk CMOS Device Optimization for High-Speed and Ultra-Low Power Operations,” 49th IEEE International MidWest Symposium on Circuits and Systems, Puerto Rico, USA, August 6-9, 2006, pp. 221-225.
J. Nyathi, R. R. Rydberg and J. G. Delgado-Frias, “Wave-Pipelining the Global Interconnect to Reduce the Associated Delays,” 49th IEEE International MidWest Symposium on Circuits and Systems, Puerto Rico, USA, August 6-9, 2006, pp. 208-212.
K. Prajapati and J. Nyathi, “An Efficient Key Update Scheme For Wireless Sensor Networks,”  The 2006 International Conference on Wireless Networks (ICWN'06), Las Vegas, USA, June 26-29, 2006, pp. 8-14.

2005

V. Beiu, J. Nyathi and S. Aunet, “Sub-Pico Joule Switching High Speed CMOS Circuits are Feasible, The Second International Conference on Innovations in Information Technology (IIT’05), Dubai, UAE, September 26-28, 2005.
J. E. Levy, J. Nyathi, and J. G. Delgado-Frias, “High-Performance Parallel Addition Using Hybrid Wave-Pipelining,” 2005 IEEE International Midwest Symposium on Circuits and Systems, Cincinnati , Ohio , August 7-10, 2005 .
V. Beiu, S. Aunet , J. Nyathi, R. R. Rydberg III, and A. Djupdal, “On the Advantages of Serial Architectures for Low-Power Reliable Computations,” 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), Samos , Greece , July 23-25, 2005 .
V. Beiu, S. Aunet, R. R. Rydberg III, A. Djupdal, and J. Nyathi, “The Vanishing Majority Gate: Trading Power and Speed for Reliability,” IEEE International Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures (NANOARCH’05), Palm Springs, CA, May 1, 2005.
R. R. Rydberg, J. Nyathi and J. G. Delgado-Frias, “A Distributed FIFO Scheme for on Chip Communication,” 2005 IEEE International Symposium on Circuits and Systems (ISCAS), Kobe , Japan, pp. 1851-1854 , May 23 – 26, 2005.

2004

V. Beiu, U. Rückert, S. Roy , and J. Nyathi, “On Nanoelectronic Architectural Challenges and Solutions,” 4th IEEE Conference on Nanotechnology, Munich Germany , pp. 628-631, 16-19 August, 2004.
J. Nyathi, V. Beiu, S. Tatapudi and D. J. Betowski, “A Charge Recycling Differential Noise Immune Perceptron,” Proceedings 2004 IEEE International Joint Conference on Neural Networks, Vol. 3, Hungary, Austria, pp. 1995 – 2000, July 25-29, 2004.
J. Levy and J. Nyathi, “A High Performance, Low Area Overhead Carry Lookahead Adder,” (World Academy of Science) Proceedings of the International Conference on VLSI, Las Vegas, Nevada, pp. 417-423, June 21-24, 2004.
R. R. Rydberg, J. Nyathi and J. G. Delgado-Frias, “A Distributed FIFO Scheme for System on Chip Inter-Component Communication,” (World Academy of Science) Proceedings of the International Conference on VLSI, Las Vegas, Nevada, pp. 536-540, June, 21-24, 2004.

2003

J. Nyathi , J. G. Delgado-Frias, and J. Lowe, “ A High Performance, Hybrid Wave-Pipelined Linear Feedback Shift Register with Skew Tolerant Clocks,” The Forty-Sixth IEEE International Midwest Symposium on Circuits and Systems, Cairo, Egypt, pp. 1384-1387, December 27-30, 2003.

2001 and Prior

J. G. Delgado-Frias and J. Nyathi, “A Hybrid Wave-Pipelined Network Router,” IEEE Computer Society Annual Workshop on VLSI (WVLSI 2001), Orlando , Florida , pp. 165-170, April 2001.
J. G. Delgado-Frias and J. Nyathi, “A Wave-Pipelined CMOS Associative Router For Communication Switches,” 2000 IEEE International Symposium on Circuits and Systems, Geneva, Switzerland, pp. 391-394, May 2000.
J. G. Delgado-Frias, J. Nyathi, and L. Bhuyan, “A Wave-Pipelined Router Architecture Using Ternary Associative Memory,” IEEE Tenth Great Lakes Symposium on VLSI,  Chicago, Illinois, pp. 67-70, March 2000.
J. G. Delgado-Frias, A. Yu, and J. Nyathi "A Dynamic Content Addressable Memory Using A 4-Transistor Cell," IEEE Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications,  Puerto  Vallarta, Mexico,  pp. 110-113, July 1999.
J. G. Delgado-Frias and J. Nyathi, "A High Performance Wave-Pipelined Router," 12th International Conference on Control Systems and Computer Science, Bucharest, Romania, Vol. II, pp. 151-156, May 1999.
J. Nyathi and J. G. Delgado-Frias, "Self-timed Refreshing Approach for Dynamic Memories," Eleventh Annual IEEE International ASIC Conference, Rochester, New York, pp. 169-173, September 1998.
J. Nyathi and J. G. Delgado-Frias, "Ternary Decoupled Dynamic Content Addressable Memories," IEEE Second International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, Guanajuato, Mexico, pp. 129-132, July 1998.
J. G. Delgado-Frias and J. Nyathi, "A VLSI High-Performance Encoder with Priority Lookahead," IEEE Eighth Great Lakes Symposium on VLSI, Lafayette , Louisiana , pp. 59-64 February 1998.
J. G. Delgado-Frias, J. Nyathi, C. L. Miller, and D. H. Summerville, "A VLSI Interconnection Network Router Using A D-CAM with Hidden Refresh," IEEE Sixth Great Lakes Symposium on VLSI, Ames, Iowa, pp. 246-251, March 1996.