VLSI RESEARCH PROJECTS
Scaling of silicon technologies has for several decades afforded digital circuits/systems designers with improved performance particularly speed, however, as we approach the physical limits of silicon, we are confronted with increased leakage currents. Leakage power is viewed as having the potential to exceed dynamic power with further scaling. In addition interconnect delays have become dominant leading to a view point that regards digital systems' performance as being communication bound instead of being computation bound. Despite these issues silicon based electronics remain  widely popular and device miniaturization has given rise to new computing needs. It is envisioned that in the very near future computers will  anticipate our needs. In light of these view points our research seeks to provide lasting solutions that would enable prolonged use of silicon based electronics, by proposing design methods that would potentially serve to bridge silicon based systems with those designed to use emerging technologies/devices. To this end we address the issues of increased leakage power and the dominant interconnect delays. 

 

 
 
Brent Bero's research focused on techniques involving operating transistors in weak inversion (subthreshold region).  It has already been shown that  the leakage currents can be used to drive logic instead of working to limit them. Power supply voltages are scaled to below threshold voltages resulting in minute currents (nano-Amp to pico-Amp currents). Ultralow power systems have been demonstrated however no attempts have been made to improve speeds for these circuits. We propose tunable subthreshold circuits that can operate at above threshold power supply voltages as well.   These circuits would be critical in the design of digital systems intended to anticipate our needs particularly the microcontrollers designed as engines for  embedded sensor networks.
 
 
Ray Robert Rydberg has performed an examination of the interconnect delays and proposed I/O circuits with the potential for use in interfacing  multiple clock domain IPs of System-on-Chip. He is extending this work to evaluate the impact of the interconnect in the subthreshold regime concentrating particularly on issues relating to the reliability of systems operating in subthreshold.
 
 
Ryan McKinley evaluated parallel and serial architectures of the subthreshold regime. Reduced power supply voltages are likely to further discourage use of long interconnects between communicating modules of a sub-system/system and would thus dictate that serial architectures be used instead of parallel ones. Extensive evaluation of parallel and serial micro-architectures operating in the subthreshold regime is underway.