|
Syllabus Professor: Email: Phone: Office: Office
Hours: Class
Times and Location: |
Course Name: |
|
Syllabus Insert objectives here. 1. Fundamentals of Computer Design (Chapter 1) 1.1 Performance 1.2 Principles of Computer Design 1.3 Performance and Cost 2. Pipelining and Instruction Set (Appendices A and B) 2.1 Basic Pipeline 2.2 Pipeline hazards: structural, data, and control. 2.3 Pipeline implementation issues 2.4 Case study: MIPS R4000 pipeline 2.5 Instruction set architectures 2.6 Operand storage, type and size 2.7 Examples of instruction sets (MIPS and DLX) 3. Instruction-Level Parallelism and its Limitations (Chapters 2 & 3) 3.1 Instruction-level parallelism (ILP) 3.2 Dynamic scheduling 3.3 Branch Prediction 3.4 Multiple instruction issue 3.5 Thread level parallelism 3.6 Case study: Intel Pentium 4 4. Multiprocessors (multi-core) and Thread Level Parallelism (Chapter 4) 4.1 Symmetric shared-memory architectures 4.2 Distributed shared memory 4.3 Coherence and synchronization 4.4 Case study: SUN T1 multiprocessor 5. Memory Hierarchy Design (Chapter 5) 5.1 Principle of locality 5.2 Memory hierarchy and cache memory 5.3 Cache performance optimizations 5.4 Virtual Memory
2 Partial Exams (25% each)
50%
Project
15%
Homework
15%
Final Exam
20%
Back
To My Homepage
Syllabus | Schedule | Notes | Assignments | Resources | Laboratories Contact
insert name
at professor@eecs.wsu.edu
( x5555 ) |
|