Syllabus
 Objectives
 Main topics
 Grade

Schedule

Notes

Assignments

Resources

Laboratories

Professor:
Jose Delgado-Frias

Email:
jdelgado@eecs.wsu.edu

Phone:
(509)335-1156

Office:
EME 502

Office Hours:
Wednesday                  10-11:30AM

Class Times and Location:
Tuesday/Thursday
10:35–11:50am   Sloan 5


Course Name:

Syllabus

Objectives

To provide a background on advanced computer architecture. The main focus of this course is advanced processor design and evaluation using case studies. A number of architectural alternatives are described and evaluated using quantitative approaches.



Main topics

1. Fundamentals of Computer Design                                                                     (Chapter 1)

1.1   Performance

1.2   Principles of Computer Design

1.3   Performance and Cost

2. Memory Hierarchy Design                                                                                    (Chapter 5)

            2.1 Principle of locality

            2.2 Memory hierarchy and cache memory

            2.3 Cache performance optimizations

            2.4 Virtual Memory

3. Pipelining and Instruction Set                                                                  (Appendices A & B)

            3.1 Basic Pipeline

            3.2 Pipeline hazards: structural, data, and control.

            3.3 Pipeline implementation issues

            3.4 Case study: MIPS R4000 pipeline

            3.5 Instruction set architectures

            3.6 Operand storage, type and size

            3.7 Examples of instruction sets (MIPS and DLX)

4. Instruction-Level Parallelism and its Limitations                                            (Chapters 2 & 3)

            4.1 Instruction-level parallelism (ILP)

            4.2 Dynamic scheduling

            4.3 Branch Prediction

            4.4 Multiple instruction issue

            4.5 Thread level parallelism

            4.6 Case study: Intel Pentium 4

5. Multiprocessors (multi-core) and Thread Level Parallelism                                  (Chapter 4)

            5.1 Symmetric shared-memory architectures

            5.2 Distributed shared memory

            5.3 Coherence and synchronization

            5.4 Case study: SUN T1 multiprocessor



Grade

                  2 Partial Exams (25% each)                       50%

                  Project                                                      10%

                  Homework                                                 20%

                  Final Exam                                                20%

 

 

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