Syllabus

 

 

 

 

 

 

Professor:
Jose Delgado-Frias

Email:
jdelgado@eecs.wsu.edu

Phone:
(509)335-1156

Office:
EME 502

Office Hours:
Tuesday                  10AM-12noon

Class Times and Location:
M, W, F 9:10-10AM      Sloan 233
EE334 Computer Architecture      (Spring 2012)

Objectives: To provide a sound background on computer architecture. The main focus of this course is processor design and evaluation with case studies. A number of architectural alternatives are described and evaluated using quantitative approaches.

Homework Assignments

Homework 1: Assignment. Code_shell. Example  (Due: January 27, 9:10AM)

Homework 2: Adder Delay (Due: February 8, 9:10AM)

Homework 3: FP_TaylorSeries (Due: February 13, 9:10AM)

Homework 4: Datapath (Due: February 22, 9:10AM)

Homework 5: Pipeline 1 (Due: March 21, 9:10AM) solution HW 5

Homework 6: Pipeline 2 (Due: March 28, 9:10AM) solution HW 6

Homework 7: Pipeline 3 (Due: April 4, 9:10AM) solution HW 7

Homework 8: Pipeline 4 (Due: April 9, 9:10AM) solution HW 8

SAMPLE:  trace_sample

Project: Description
Benchmark Traces


Final Exam: May 4, 2012.  9AM-10AM  (Major topics)

 

Student Feedback



Handouts

Chapter 1: Introduction
Chapter 2: Instruction Set Architecture
Chapter 3: Arithmetic and Floating Point
Chapter 4: Processor (Part A)
Chapter 4: Processor (Part B)  (Author: Peter Ashenden)
Chapter 5: Memory  (Author: Peter Ashenden)

 

Contact: jdelgado@eecs.wsu.edu ( 509/335-1156 )
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