JOURNAL
PAPERS
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J.
G. Delgado-Frias and G. B. Ratanpal, A VLSI Crossbar Switch with Wrapped Wave
Front Arbitration, IEEE
Transactions on Circuits and Systems, I: Fundamental Theory and Applications,
vol. 50, no. 1, pp.135-141, January 2003. (PDF)
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J.
Nyathi and J. G. Delgado-Frias, A Hybrid Wave-Pipelined Network Router, IEEE Transactions on Circuits and Systems,
I: Fundamental Theory and Applications, vol.49,
no. 12, pp.1764-1772, December 2003. (PDF)
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S. Vassiliadis,
M. Zhang, and J. G. Delgado-Frias, Elementary Function Generators for
Neural Network Emulators, IEEE Transactions on Neural Networks,
vol. 11, no. 6, pp. 1438-1449, November 2000. (PDF)
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J. G. Delgado-Frias
and J. Nyathi, A High-Performance Encoder with Priority Lookahead,
IEEE
Transactions on Circuits and Systems, I: Fundamental Theory and Applications,
vol.
47, no. 9, pp. 1390-1393, September 2000.(PDF)
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V. C. Aikens,
II, J. G. Delgado-Frias, G. G. Pechanek, and S. Vassiliadis, A Neuro-Emulator
with Embedded Capabilities for Generalized Learning, Journal of
Systems Architecture, vol. 45, no.11, pp.1119-1143, July 1999. (PDF)
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A. DeLuca,
J. G. Delgado-Frias, and J. Hernandez, A Survey on Routers for Parallel
Architectures, Int. Journal on Instrumentation and Development,
vol.
8, no. 1, pp. 3-11, 1999.
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J. G. Delgado-Frias,
J. Nyathi, and D. H. Summerville, A Programmable Dynamic Interconnection
Network Router with Hidden Refresh, IEEE Transactions on Circuits
and Systems I: Fundamental Theory and Applications, vol. 45, no.11,
pp.1182-1190, November 1998.(PDF)
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D. H. Summerville,
J. G. Delgado-Frias, and S. Vassiliadis, Executing Tree Routing Algorithms
on a High-Performance Pattern Associative Router, Journal of Systems
Architecture, vol. 44, no. 11, pp. 849-865, August 1998. (PDF)
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C-Y. Lu,
J. G. Delgado-Frias, and W. Lin, A Clustering and Genetic Scheme for
Large TSP Optimization Problems, Cybernetics and Systems: An International
Journal, vol. 19, no. 2, pp. 137-157, March 1998.
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A. E. Harvin,
III and J. G. Delgado-Frias, A VLSI Highly Pipelined Computing/ Communicating
Tree Structure, Journal of Microelectronic Systems Integration,
vol.
4, no. 4, pp. 237-248, December 1996.
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M. Zhang,
S. Vassiliadis, and J. G. Delgado-Frias, Sigmoid Generator for Neural
Computing Using Piece Wise Approximations, IEEE Transactions on
Computers, vol. 45, no. 9, pp. 1045-1049, September 1996.
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G. Triantafyllos,
S. Vassiliadis and J. G. Delgado-Frias, Software Metrics and Microcode
Development: A Case Study, Journal of Software Maintenance: Research
and Practice,
vol. 8, pp. 199-224, 1996.
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D. H. Summerville,
J. G. Delgado-Frias, and S. Vassiliadis, A Flexible Bit-Associative
Router for Interconnection Networks, IEEE Transactions on Parallel
and Distributed Systems, vol. 7, no. 5, pp. 477-485, May 1996. (PDF)
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W. Lin, J.
G. Delgado-Frias, D. C. Gause, and S. Vassiliadis, A Hierarchical Genetic
Algorithm for the TSP, Journal of Mathematical Modelling and Scientific
Computing,
vol. 6, April 1996.
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H. D. Johnson,
J. G. Delgado-Frias, S. Vassiliadis, and D. M. Green, A Flexible Modeling
Approach for Assessing Multiprocessor Computers, Int. Journal of
Modelling and Simulation,
1996.
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J. Park,
S. Vassiliadis, and J. G. Delgado-Frias, Flexible Oblivious Router Architecture,IBM
Journal of Research and Development, vol. 39, no. 3, pp. 315-334, May
1995.
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W. Lin, J.
G. Delgado-Frias, D. C. Gause, and S. Vassiliadis, A Hybrid Newton-Raphson
Genetic Algorithm for the Traveling Salesman Problem, Cybernetics
and Systems: An International Journal, vol. 26, no. 4, pp. 387-412,
1995.
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W. Chu, S.
Vassiliadis, and J. G. Delgado-Frias, The Multi-Associative Target Buffer:
A Cost Effective BTB Mechanism, Microprocessing and Microprogramming
Journal,
vol. 41, no. 3, pp. 211-225, 1995.
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J. G. Delgado-Frias,
S. Vassiliadis, H. D. Johnson, D. H. Summerville, D. M. Green, and A. De
Luca,A Processing Unit for Parallel Computer Organizations,
Int.
Journal on Instrumentation and Development, vol. 3, no. 4, pp. 20-32,
1994.
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J. G. Delgado-Frias,
S. Vassiliadis, C-L. Chu, and A. De Luca, DT: A Binary Tree Parallel
Computer with Distributed I/Os, Int. Journal on Instrumentation
and Development, vol. 3, no. 4, pp. 33-42, 1994.
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M. Zhang,
J. G. Delgado-Frias, and S. Vassiliadis, Table Driven Newton Scheme
for High Precision Logarithm Generation, IEE Proceedings Section
E: Computers and Digital Techniques, vol. 141, no. 5, pp. 281-292,
September 1994.
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J. G. Delgado-Frias
and D. M. Green, A Finite Difference Wafer-Scale Machine with Time-Redundant
Fault Tolerance, Journal of Microelectronic Systems Integration,
vol.
2, no.1, pp. 3-12, March 1994.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, Folded Axon/Dendrite Tree Neurons:
A New Model for the Neural Paradigm, Valgo, La revue de l'Association
des Connexionnistes, no. 94-1, pp. 45-55, June 1994.
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C. Chang,
S. Vassiliadis, and J. G. Delgado-Frias, An Investigation of Binary
CLA and Ripple CMOS Adder Designs, Microprocessing and Microprogramming
Journal, vol. 40, pp. 1-21, 1994.
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S.
Vassiliadis, G. Pechanek, and J. G. Delgado-Frias, SPIN: The Sequential
Pipelined Neuro-emulator, International Journal on Artificial Intelligence
Tools, vol. 2, no. 1, pp. 117-132, 1993.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, Many-SNAP, IBM Technical
Disclosure Bulletin, vol. 34, No. 10A, pp. 100-106, March 1992.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, Shared Output SNAP,
IBM
Technical Disclosure Bulletin, vol. 34, No. 10A, pp. 107-110, March
1992.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, Digital Neural Emulators Using
Tree Accumulation and Communication Structures, IEEE Transactions
on Neural Networks, vol. 3, no. 6, pp. 934-950, November, 1992.
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J. G. Delgado-Frias,
S. Vassiliadis, and J. Goshtasbi, Semantic Network Architectures: An
Evaluation, International Journal on Artificial Intelligence Tools,
vol.
1, no. 1, pp. 57-83, 1992 (invited paper).
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J. G. Delgado-Frias
and W. R. Moore, A Semantic Network Architecture for Knowledge Base
Processing, Int. Journal for Engineering Application of Artificial
Intelligence, vol. 3, pp. 4-10, March 1990.
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J. G. Delgado-Frias
and W. R. Moore, Parallel Computer Architectures for AI Semantic Network
Processing, Int. Journal on Knowledge Based Systems, vol. 1,
no. 5, pp. 259-265, December 1988.
INTERNATIONAL
CONFERENCE PAPERS
- M.
J. Myjak and J. G. Delgado-Frias, A Two-Level Reconfigurable Architecture
for Digital Signal Processing, The 2003 International Conference on
VLSI (VLSI'03), Las Vegas, Nevada, June 23-26, 2003.(PDF)
- D.
R. Blum and J. G. Delgado-Frias, A Fault-Tolerant Memory-Based Cell for a
Reconfigurable DSP Processor, The 2003 International Conference on
VLSI (VLSI'03), Las Vegas, Nevada, June 23-26, 2003.
- F.
L. Anderson and J. G. Delgado-Frias, A Reconfigurable Crossbar Switch for
a DSP Array, The 2003 International Conference on VLSI (VLSI'03), Las
Vegas, Nevada, June 23-26, 2003.
- J.
G. Delgado-Frias, M. J. Myjak, F. L. Anderson, and D. R. Blum, A
Medium-Grain Reconfigurable Cell Array for DSP Applications, IASTED
International Conference on Circuits, Signal and Systems (CSS 2003), Cancun,
Mexico, pp. 231-236, May 2003. (PDF)
- S.
Tatapudi, and J. G. Delgado-Frias, A VLSI Self-Compacting Buffer for
Priority Queue Scheduling, IASTED International Conference on
Circuits, Signal and Systems (CSS 2003), Cancun, Mexico, pp. 310-315,
May 2003. (PDF)
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J.
J. Rooney, J. G. Delgado-Frias and D. H. Summerville, An Associative Ternary
Cache for IP Routing, Int. Conf. on Communications and Computer Networks
(CCN 2002), Cambridge, Massachusetts, Nov. 4-6, 2002. (PDF)
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J. G. Delgado-Frias
and J. Nyathi, A Hybrid Wave-Pipelined Network Router,
IEEE Annual
Workshop on VLSI, Orlando, Florida, April 19-20, 2001.(PDF)
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J. G. Delgado-Frias
and G. Ratanpal, A VLSI Wrapped Wave Front Arbiter for Crossbar Switches,
Great
Lakes Symposium on VLSI, West Lafayette, Indiana, March 22-23, 2001.
(PDF)
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V.
Skormin, J. G. Delgado-Frias, D. McGee, J. Giordano, L. Popyack, V.Gorodetski,
and A.Tarakanov, BASIS: Biological Approach to System Information Security,International
Workshop on Mathematical Methods, Models and Architectures for Computer
Networks Security, St. Petersburg, Russia, May 21-23, 2001.(PDF)
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J. G. Delgado-Frias
and J. Nyathi, A Wave-Pipelined CMOS Associative Router For Communication
Switches, ISCAS-2000 Int. Symposium on Circuits and Systems,
Geneva, Switzerland, pp. I-391 – I-394, May 2000. (PDF)
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J. G. Delgado-Frias,
J. Nyathi, and L. Bhuyan, A Wave-Pipelined Router Architecture Using
Ternary Associative Memory, IEEE Tenth Great Lakes Symposium on
VLSI, Chicago, Illinois, pp. 67-70, March 2000.
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J. G. Delgado-Frias
and A. Jafri, An Associative Self-Compacting Buffer for Communication
Switches, IEEE Third Int. Workshop on Design of Mixed-Mode Integrated
Circuits and Applications, pp. 102-105, Puerto Vallarta, Mexico, July
1999. (PDF)
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J. G. Delgado-Frias,
A. Yu, and J. Nyathi, A Dynamic Content Addressable Memory Using a 4-transistor
Cell, IEEE Third Int. Workshop on Design of Mixed-Mode Integrated
Circuits and Applications, pp. 110-113, Puerto Vallarta, Mexico, July
1999. (PDF)
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J. G. Delgado-Frias
and J. Nyathi, A High-Performance Wave-Pipelined Router,12th
Int. Conf. on Control Systems and Computer Science, Bucharest, Romania,
Vol. II, pp. 151-156, May 26-29, 1999.
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J. Nyathi
and J. G. Delgado-Frias, Self-Timed Refreshing Approach for Dynamic
Memories, 11th Annual IEEE International ASIC Conference, Rochester,
New York, pp. 169-173, September 1998. (PDF)
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J. Nyathi
and J. G. Delgado-Frias, Ternary Decoupled Dynamic Content Addressable
Memories, IEEE Second Int. Workshop on Design of Mixed-Mode Integrated
Circuits and Applications, pp. 129-132, Guanajuato, Mexico, July 1998.
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J. G. Delgado-Frias
and J. Nyathi, A VLSI High-Performance Encoder with Priority Lookahead,
IEEE Eighth Great Lakes Symposium on VLSI, pp. 59-64, Lafayette, Louisiana,
February 1998. (PDF)
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J. G. Delgado-Frias
and R. Diaz, A VLSI Self-Compacting Buffer for DAMQ Communication Switches,IEEE
Eighth Great Lakes Symposium on VLSI,
pp. 128-133, Lafayette, Louisiana,
February 1998. (PDF)
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A. E. Harvin,
III and J. G. Delgado-Frias, A Dictionary Machine Emulation on a VLSI
Computing Tree System, IEEE Eighth Great Lakes Symposium on VLSI,
pp.
134-139, Lafayette, Louisiana, February 1998.
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D. G. Rice,
J. G. Delgado-Frias, and D. H. Summerville, A Pattern-Associative Router
for Interconnection Network Adaptive Algorithms, Euro-Par’96 The
European Conference on Parallel Processing, Lyon, France, August 27-29,
1996. Appears in Lecture Notes in Computer Science, vol. 1123, pp. 213-217,
Berlin: Springer, 1996.
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V. C. Aikens,
J. G. Delgado-Frias, G. G. Pechanek, and S. Vassiliadis, Parallel Pipelined
DSP Processing Core, Proceedings of the 39th Midwest Symposium on
Circuits and Systems, Ames, Iowa, pp. 81–84, August, 1996.
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V. C. Aikens,
J. G. Delgado-Frias, S. Barber, G. G. Pechanek, and S. Vassiliadis,
A
Neuro-Architecture with Learning and Virtual Emulation Capabilities,IEEE
Int. Conference on Neural Networks (ICNN ‘96), pp. 1355-1360, Washington,
D.C., June 1996.
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J. G. Delgado-Frias,
J. Nyathi, C. L. Miller, and D. H. Summerville, A VLSI Interconnection
Network Router Using a D-CAM with Hidden Refresh, IEEE Sixth Great
Lakes Symposium on VLSI, pp. 246-251, Ames, Iowa, March 1996.
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D. G. Rice,
J. G. Delgado-Frias, and D. H. Summerville, A Pattern-Associative Router
for Adaptive Algorithms in Hypercube Networks, Int. Conference on
Parallel and Distributed Computing Systems, pp. 238-242, Washington,
D.C., October 1995.
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V. C. Aikens,
S. Barber, J. G. Delgado-Frias, G. G. Pechanek, and S. Vassiliadis,
A
Neuro-Architecture with Embedded Learning, Int. Conference
on Parallel and Distributed Computing Systems, pp. 103-106, Washington
D.C., October 1995.
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A. E. Harvin,
III and J. G. Delgado-Frias, A VLSI Processing and Communicating Pipelined
Tree for Parallel Computing, Int. Conference on Parallel and
Distributed Computing Systems, pp. 455-458, Washington D.C., October
1995.
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M.A Partida,
A. De Luca, J.G. Delgado-Frias, J. Goddard, R.U. Parrazales, High Precision
Programmable Adaptive Digital Frequency Multiplier, Proceedings
of the 38th Midwest Symposium on Circuits and Systems, Volume: 1, pp.
385 –388, 1995.
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W. Lin, J.
G. Delgado-Frias, D. C. Gause, and S. Vassiliadis, Solving the Traveling
Salesman Problem Using a Hybrid Genetic Algorithm Approach, Int.
Conference on Artificial Neural Networks in Engineering (ANNIE ‘94),
pp. 1069-1074, Rolla, Missouri, November 1994.
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J. Park,
B. O’Krafka, S. Vassiliadis, and J. G. Delgado-Frias, Design and Evaluation
of a DAMQ Multiprocessor Network Switch with Self-Compacting Buffers,IEEE
Supercomputing ‘94, The Conference on High Performance Computing and Communications,
pp.
713-722, Washington, DC, November 14-18, 1994. (PDF)
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J. G. Delgado-Frias,
G. G. Pechanek, S. Vassiliadis, H. Ding and W. Lin, Organization and
Implementation of a Highly Pipelined Neuroemulator, 14th IMACS World
Congress on Computation and Applied Mathematics, pp. 661-664, Atlanta,
Georgia, July 1994.
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G. G. Pechanek,
S. Vassiliadis, J. G. Delgado-Frias, and G. Tryantafillos, Scalable
Completely Connected Digital Neural Networks, Conference on Neural
Networks at the IEEE World Congress on Computational Intelligence,
pp. 2078-2083, Orlando, Florida, June 26-July 2, 1994.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, The Folded Axon/Dendrite Tree
Neuron Model, Conference on Neural Networks at the IEEE World
Congress on Computational Intelligence, pp. 1397-1402, Orlando, Florida,
June 26-July 2, 1994.
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W. Lin, J.
G. Delgado-Frias, G. G. Pechanek, and S. Vassiliadis, An Investigation
of the Precision Impact on the Hopfield-Tank Neural Network Model for the
TSP, Conference on Neural Networks at the IEEE World Congress on
Computational Intelligence, pp. 4523a-4528, Orlando, Florida, June
26-July 2, 1994.
-
W. Lin, J.
G. Delgado-Frias, G. G. Pechanek, and S. Vassiliadis, Impact of Energy
Function on a Neural Network Model for Optimization Problems,
Conference on Neural Networks at the IEEE World Congress on Computational
Intelligence, pp. 4518-4523, Orlando, Florida, June 26-July 2, 1994.
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D. H. Summerville,
J. G. Delgado-Frias, and S. Vassiliadis, A High Performance Pattern
Associative Router for Tree Topologies, IEEE Eighth International
Parallel Processing Symposium, pp. 541-545, Cancun, Mexico, April 1994.
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J. G. Delgado-Frias,
W. R. Sze, D. H. Summerville, and V. Aikens, A CAM-Based VLSI Router
for Multiprocessor Machines, IEEE Fourth Great Lakes Symposium on
VLSI, pp. 124-129, Notre Dame, Indiana, March 1994.
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J. G. Delgado-Frias,
S. Vassiliadis, H. D. Johnson, D. H. Summerville, D. M. Green, and A. DeLuca,
A
Processor for MIMD Machines, Mexicon 1994 IEEE Int. Conf. on Electrical,
Electronics, and Computer Engineering, pp. 94-112, Puebla, Mexico,
February, 1994.
-
J. G. Delgado-Frias
and D. H. Summerville, The Impact of Microelectronics on Parallel Computer
Systems, Mexicon 1994 IEEE Workshop on Recent Advances in Microelectronics,
pp. 1-12, Puebla, Mexico, February, 1994.
-
H. D. Johnson,
J. G. Delgado-Frias, S. Vassiliadis, and D. M. Green, A Petri Net Technique
for Assessing Performance of Multiprocessor Architectures,Int. Workshop
on Performance Evaluation of Parallel Systems, pp. 43-50, Univ. of
Warwick, England, November 29-30, 1993.
-
S. Vassiliadis,
J. G. Delgado-Frias, and M. Zhang, First Order Piece-Wise Sigmoid Generators,
Int. Conference on Artificial Neural Networks in Engineering (ANNIE ‘93),
pp.
77-82, Rolla, Missouri, November 1993.
-
G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, Multiple-Fold Clustered Processor
Mesh Array, Fifth NASA Symposium on VLSI Design,
pp. 8.4.1-8.4.11,
Albuquerque, New Mexico, November 1993.
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G. G. Pechanek,
J. G. Delgado-Frias, and S. Vassiliadis, A Massively Parallel Diagonal-Fold
Mesh Array Processor, 1993 International Conference on Application
Specific Array Processors, Venice, Italy, October 1993.
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W. Lin, J.
G. Delgado-Frias, S. Vassiliadis, and G. G. Pechanek, Machine and Precision
Influence on the Hopfield-Tank Model for the TSP, Int. Joint Conference
on Neural Networks, pp. 1516-1519, Nagoya, Japan, October 1993.
-
S. Vassiliadis,
J. G. Delgado-Frias, and M. Zhang, High Performance with Low Implementation
Cost Sigmoid Generators, Int. Joint Conference on Neural Networks,
pp. 1931-1934, Nagoya, Japan, October 1993.
-
S. M. Barber,
J. G. Delgado-Frias, S. Vassiliadis, and G. G. Pechanek, SPIN-L: Sequential
Pipelined Neuroemulator with Learning Capabilities, Int. Joint Conference
on Neural Networks, pp. 1927-1930, Nagoya, Japan, October 1993.
-
J. Park,
S. Vassiliadis, and J. G. Delgado-Frias, Router Architecture for Oblivious
Routing Algorithms, 2nd Int. Conference on Parallel Computing Technologies
(PaCT-93), pp. 199-209, Obninsk, Russia, August 30 - September 4, 1993.
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A. Ahmed,
J. G. Delgado-Frias, and D. M. Green, Twisted and Randomized Interconnection
Network for Multiprocessing Computers, 9th Int. Conference
on
Systems Engineering, pp. 390-394, Univ. of Nevada, Las Vegas, 14-16
July 1993.
-
G. Triantafyllos,
S. Vassiliadis and J. G. Delgado-Frias, Analyzing Error-Prone Microcode
Modules, 10th Int. Conf. on Testing Computer Software,
pp. 101-110,
Washington, DC, June 14-17, 1993.
-
S. Vassiliadis,
G. Triantafyllos, and J. G. Delgado-Frias, Defects and System Simulation:
An Empirical Analysis, European Simulation Multiconference,
pp.
75-79, Lyon, France, June 7-9, 1993.
-
G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, Review of Digital Emulators
Using Tree Accumulation and Communication Structures, ITC Conference
on Neural Networks, East-Fishkill, New York, pp. 160-164, 1992.
-
S. Vassiliadis,
G. G. Pechanek, and J. G. Delgado-Frias, SPIN: A Sequential Pipelined
Neurocomputer, IEEE Int. Conf. on Tools for Artificial Intelligence,
pp.
74-81, San Jose, Calif., November 1991.
-
R. Payne
and J. G. Delgado-Frias, MPU: A N-Tuple Matching Processor,IEEE
Int. Conference on Computer Design: VLSI in Computers and Processors ICCD’91,
pp. 225-228, Cambridge, Mass, October 1991.
-
J. G. Delgado-Frias
and W. R. Moore, A Semantic Network Architecture for Artificial Intelligence
Applications, IEEE Int. Workshop on Tools for Artificial Intelligence,
pp.
162-167, Fairfax, Virginia, October 23-25, 1989.
-
J. G. Delgado-Frias
and W. R. Moore, A Wafer Scale Architecture for Artificial Intelligence,
IEEE First Int. Conf. on Wafer Scale Integration,
pp. 121-130, San
Francisco, Calif., January 3-5, 1989.
-
J. G. Delgado-Frias
and D. M. Green, BVE: A Wafer Scale Architecture for Differential Equation
Computations, ACM International Conference on Supercomputing,
pp. 101-107, Saint-Malo, France, July 4-8, 1988.
-
J. G. Delgado-Frias
and D. M. Green, A Multi-processor WSI Boundary Value Architecture,
IEEE
Int. Conf. on Computer Design: VLSI in Computer and Processor (ICCD),
pp. 490-493, New York, October 5-8, 1987.
-
J. G. Delgado-Frias
and I. Conteras, WaSP: A Bit-Serial WSI Processor, IEEE CompEuro:
VLSI and Computers, pp. 164-167, Hamburg, West Germany, May 11-15,
1987.
-
J. G.
Delgado-Frias and D. M. Green, A Wafer Scale Architecture for Boundary
Value Computations, IEEE CompEuro: VLSI and Computers, pp. 686-689,
Hamburg, West Germany, May 11-15, 1987.
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