List of Potential Electrical/Computer Engineering Senior Projects for 2002-2003
Sponsored by WSU Material Science Program. Contact: Robert Novotney, 335-1131, novotney@wsu.edu
2. Measurement of Paint Thickness on Composite Materials.
Sponsored by Boeing Manufacturing R&D. contact Ed Sergoyan, 425-717-3559, edward.sergoyan@pss.boeing.com
3. An
Educational Tool for Understanding Symmetrical Components in 3 Phase Power
Systems
Sponsored by the Bonneville Power Administration. Contact Karl Mitsch, 360-619-6092,
4.
Electrical Performance of Voltage Isolators for Optical Ground Wire
Applications
Sponsored by the Bonneville Power Administration. Contact Marko Istenic of WSU, istenic@eecs.wsu.edu
Sponsored by AHA and WSU. Contact Prof. Ben Belzer of WSU, 335-4970, belzer@eecs.wsu.edu
6. Effect
of Product Packaging on Electromagnetic Susceptibility
Sponsored by Schweitzer Engineering Labs. Contact Don MacArthur at SEL, 332-1890, don_macarthur@selinc.com or Robert Olsen at WSU, 335-4950, olsen@eecs.wsu.edu
7. Postdeposition Oxidation of Organic Diodes
Sponsored by WSU EECS, Contact: Patrick Pedrow, 509-335-1749, pedrow@eecs.wsu.edu,
8. ATP
Modeling of the Northwest Transmission Network
Sponsored by Schweitzer Engineering Labs. Contacts: Armando Guzman and Luis Perez, 332-1890, armando@selinc.com
9. Analog
Circuit for Ratio Measurements
Sponsored by
10. Video
Functional Tester or Duplex Voice Coder
Sponsored by Agilent Technologies,
Sponsored by Boeing, Contact T.H. Friddel, (253)
773-9277, thomas.h.friddell@boeing.com
Sponsored by Boeing Connexions, Contact Jim Handy, (949)-790-1556.
Sponsored by WSU EECS, contact Dr. Mohamed A. Osman, 335-2301, osman@eecs.wsu.edu
14. Bi-directional Computer Modem
Sponsored by Tektronix, Contact Jeff Earls, (503) 627-4127 jeff.earls@tek.com
15. Maze Following Robot, FPGA
Based Computer System or Motion Tracking Camera System
Sponsored by Digilent, Contact Clint Cole, 335-1448, ccole@eecs.wsu.edu
16. Performance Evaluation of PC’s
Sponsored by Hewlett Packard, contact Rick Hoover, (208) 396-7457, rick_hoover@hp.com
Project
Descriptions
I.
Vanadates Crystals
Vanadates
crystals, YVO4, have major applications in the optical laser
field. The
The manufacturing process is in transition from a highly labor intensive process based entirely on manual observation and adjustments to computer controlled process. A portion of the project will entail the instrumentation, monitoring, and data collection of various process parameters such as, material melt temperatures, cooling water flows and temperatures, Nitrogen gas pressure and consumption, Oxygen levels, electrical power consumption, crystal rotation, crystal withdrawal rate, and crystal growth rate. Additional data points may be defined as the project progresses.
This project will entail the computer interfacing with the necessary instrumentation such, Infrared sensors, RF monitors, and video monitors for melt condition recognitions to obtain real time data. Since Labview is the data collection and control program used by II-VI, it will be the basic program format used for this project.
The installation of a two-color camera system for pattern recognition to identify melt form changes associated with changes in processing parameters will be an advance goal of this project.
Personnel Requirements: Following are some of the traits that are considered essential for personnel assigned to this project. The team may be comprised of individuals that excel in a specific area of technical expertise.
- Experience with the LabView programming system or other programming software
- Interest in computer interfacing of process parameters sensors
- Understanding of electrical engineering theory and fundamentals, and interest in their application
- Interest in instrumentation and process controls
- Interest in the application of Radio Frequency theory as it applies to induction furnace heating
- Interest in hands on construction and installation of instrumentation and electrical components
II. Measurement of Paint on Composites
Background and problem statement: Aircraft paint systems are being required for composite materials that are either carbon fiber epoxy honeycomb and multi-ply structures or fiberglass with sub-surface metallic coatings. More control surfaces are being manufactured as complete subassemblies using primarily composite materials.
Boeing currently has very limited paint thickness measurement methods that work directly on the composite materials used on Boeing aircraft. Several commercial ultrasound paint thickness measurement device have been evaluated and tested on composite rudders.
Proper control of paint thickness insures uniformity for enhanced control surface performance while limiting weight on the aircraft. This is particularly important for rudder balance. This project is aimed at developing new methods for measurement and control of paint thickness on all substrate materials. The project is an extension of feasibility studies done at WSU in early 2002, where several methods returned very encouraging results for measurement of paint on composites. The focus of this work is to develop tools that can be packaged for use on flat and mildly curved surfaces outside of a laboratory environment.
Project goal and objectives: The project goal of this program is the development of a measurement device for measuring paint thickness on composite rudders and control surfaces.
We will try to develop tools for both flat and curved surfaces and characterize the deviation caused by mild curvature. The tools will be compact, intrincially safe and capable of a successful measurement for a range of primer thickness between 0.0003 inches to 0.001 inches on a surface. The measurement will be made from one side of the surface. Uniform pressure loading will be applied to the tools in a fast and repeatable fashion.
Approach: The devices are already on hand in laboratory form. They have been tested on calibration panels. The approach is to repackage the laboratory devices for further experiments to verify the reliability of the techniques. If time and production schedule permits, the devices will be tested on at least 2 rudders while the paint layers are being applied.
Once these tests prove that these devices can measure paint thickness accurately under shop conditions, we will work to make standards that can be used to calibrate the devices.
Risks: There are some technical risks. It is possible that neither device will work for composite rudder paint thickness measurement when tested on real aircraft structures.
It is possible that the devices will work, but cannot be successfully implemented into a factory environment.
It is possible that no other useful paint thickness measurement device will be found for measurement on composite materials.
Benefits: Paint thickness measurement will verify proper weight and eliminate disassembly and balancing. Direct measurement of paint thickness will reduce waste.
Cracking failures of composite parts due to primer thickness of greater than 2 mils can be eliminated by direct measurement.
Deliverables: A system is required that can measure paint between 0.3 mil and 1 mil with high degree of accuracy.
III. An Educational Tool for Understanding Symmetrical Components in 3 Phase Power Systems
Provide an interactive educational software package
containing a graphical interface, which can be used to teach and explain the
use of symmetrical components in 3 phase power systems.
A. Project Description
In 1918, C.L. Fortescue introduced a tool for dealing with unbalanced polyphase circuits known as symmetrical components. Symmetrical components can be used to study unsymmetrical faults and associated phenomena on 3 phase power systems.
This project involves development of a software tool, which will be used to teach engineering students the relevance of symmetrical components in the analysis of three phase power systems. The result should be a stand-alone program that can be used on a pc or as an executable in a presentation. The graphical interface should allow the user to input a set of three phase vectors and the program will display the vector set and the corresponding positive, negative and zero sequence resultant vectors. The program shall also have the capability to interactively change or unbalance the vector set and observe the corresponding change in the symmetrical components. It is also desired to show the original vector set with its symmetrical component vectors additively superimposed as in Figure 1 below. There may be additions to the scope of this project as deemed necessary by BPA or the WSU project team.
Figure 1: Unbalanced vector set Va, Vb, Vc, with its symmetrical
components additively superimposed
IV.
Electrical Performance of Voltage Isolators for Optical
Ground Wire Applications
I. INTRODUCTION
Since the early 1970’s, it has been the policy of the Bonneville Power Administration to segment and insulate 500 kV overhead shield wires used in high lightning areas. Each segment of shield wire has a maximum length of approximately 15 miles. This is grounded at the center tower and is insulated from the end towers and all other towers by dead-end insulators and tower standoff insulators respectively. Such a system is illustrated in Fig. 1.
Proposed BPA Policy on Grounding of Optical Ground Wire
The Bonneville Power
Administration plans to install optical ground wire (OPGW) on some of its 500
kV transmission lines. For at least two
reasons, this will require some changes to the existing policy on grounding of
shield wire.
First, the maximum available
continuous length of OPGW and hence the maximum distance between splices is 2 –
3 miles. Since the splices must be accessible, the length of insulated sections
will be 2-3 miles rather than the 15 miles for standard overhead ground wire
(OHGW).
Second, in order that
maintenance work can be carried out safely while the line is energized, each
splice requires an accessible splice box that is mounted relatively low on the
tower and at the same potential as the tower.
Since the splice box is bonded to the tower, it must be isolated from
the magnetically induced voltages on the OPGW.
To do this, a device called an “optical isolator” (illustrated in Fig.
1.) will be installed. In this device,
the OPGW is clamped into the top and bottom ends. In the center-insulated section, the metallic
wires surrounding the optical fiber are removed and the optical fibers passed
through the insulator. The insulated
section is designed to continuously withstand the magnetically induced voltages
around the 2 –3 mile loop.
An example topology for this
type of grounding is shown in Fig. 1. In order to accommodate the splice box,
optical isolator shown in Fig. 1 augments the dead-end insulator. As in the OHGW example, the tower standoff
insulators are designed to flashover in the event of a nearby lightning
strike. In order to protect the optical
system, the optical isolator is designed to withstand these transient lightning
induced voltages.
Fig. 1.
Proposed topology for grounding of OPGW.
The Experiment
Test the optical isolator to continuous withstand voltage in
a variety of climatic conditions. Set up
the isolator in the outdoor high voltage facility lab. Continuously expose the
isolator to a 60-Hertz voltage of 2 kV using the laboratory power supply. During this time, monitor the leakage current
across the isolator’s insulated section to determine whether the insulator is
sufficient for its purpose and to determine whether flashover has occurred. Record data about weather conditions during
the entire time (i.e. temperature excursions, precipitation and humidity).
Second, perform a flashover test to ascertain whether the
isolator will be able to sustain the expected lightning induced
transients. Conducted this test at 60
Hertz using the 345 kV power supply available in the lab. Do it with both,
clean and contaminated isolator. Related
the results of this flashover test with the transient voltages expected during
a lightning strike.
Acquire, analyze and present the collected data in the forms
of histograms, tables and statistical values. Comment the results.
V. AHA Software Wireless Modem Project
The project team will design a software wireless modem that will use AHA's 4524 turbo product code evaluation board for error correction. Phase I of the project will implement 16-QAM bit-interleaved coded modulation (BICM), and will measure the power savings due to use of AHA's error correction codes. Phase II of the project will implement a simple quality-of-service (QoS) protocol, whereby BICM coded data packets will be transmitted with an automatic-repeat-request (ARQ) protocol, while speech, image, or
video packets will be transmitted with BICM only. The project will use the software radio lab (SRL) in B-26; all required software will be written in C.
Required skills: C programming, hardware/software interfacing, digital communications.
Required classes: C programming (preferably CS121-122), EE314, EE341
Recommended classes: EE432 or EE451, EE464, EE431
At least one student on the team should be enrolled in or have already taken EE432 or EE451.
VI. Effect of Product Packaging on Electromagnetic Susceptibility
Electronic products often have to pass rigorous electromagnetic susceptibility tests before they can be offered for sale to customers. Such tests involve exposing the device to an intense electromagnetic wave over a range of frequencies while it is operating. If the device properly performs the task for which it was designed during the exposure, it passes the test.
One cause of failures is penetration of electromagnetic waves through the enclosure inside which the device is packaged. Ideally, this enclosure should “shield” the fields from the sensitive electronics inside it. It has been found, however, that penetration occurs and usually is most severe over specific ranges of frequency that can be related to the physical size and design of the enclosure.
The students will design and construct several enclosures for electronic devices. The performance of these enclosures will be evaluated in Schweitzer Engineering labs new electromagnetic exposure chamber. Specifically, the electromagnetic fields inside them will be measured during exposure to intense electromagnetic fields between 80 – 1000 MHz (and possibly 1000 – 3000 MHz) and compared to the fields that exist in the absence of the enclosure. The experiments will be interpreted using theory that has been developed for studying these issues. Following this, the students will investigate methods to mitigate the penetration and will re-evaluate the performance of the enclosure after mitigation has been incorporated.
VII. Postdeposition Oxidation of Organic Diodes
Sponsored by WSU, Contact: Patrick Pedrow, 509-335-1749, pedrow@eecs.wsu.edu,
Some organic films have semiconducting properties. Many of these films are susceptible to postdepositon oxidation by atmospheric oxygen and water vapor, consequently passivation layers may be required for long device lifetimes. Diodes have been fabricated in the EECS plasma lab from thin (< 500 nm) organic films. The EE499 student will test two arrays of these organic diodes using a conventional semiconductor parameter analyzer (HP 4145). Current will be recorded in digital format as a function of applied voltage. This I(V) characteristic will be curve-fit and compared to several prospective conduction models (ohmic, space charge limited, percolation, Schottky, etc.) The student will draw conclusions on the most likely conduction mechanism. One diode array will be stored under vacuum conditions and the other array will be exposed to atmospheric conditions. The influence of oxygen and humidity will be evaluated by logging the I(V) behavior on a daily or weekly basis for these two diode arrays (one being stored in vacuum when not located at the test stand.) The mentor for this project will fabricate the diode arrays.
One constraint on this project is that the diodes must be evaluated in the fall semester.
After evaluation of the diode arrays Fall 2002, the team will design a field effect transistor to be fabricated and evaluated Spring 2003. That is, Fall semester the students become familiar with the organic film by studying the two diode arrays. Their Fall diode experience transfers to the Spring FET effort. They will also use software to design and
predict the FET behavior. The conduction model for the organic film would need to be added to the design software if the conduction mechanism is exotic.
Some organic (plastic) films have semiconducting properties. Many of these films are susceptible to postdepositon oxidation by atmospheric oxygen and water vapor, consequently passivation layers may be required for long device lifetimes. Diodes have been fabricated in the EECS plasma lab from thin (<500 nm) organic films. The EE499 student will test two arrays of these organic diodes using a conventional semiconductor parameter analyzer (HP 4145). Current will be recorded in digital format as a function of applied voltage. This I(V) characteristic will be curve-fit and compared to several prospective conduction models (ohmic, space charge limited, percolation, Schottky, etc.) The student will draw conclusions on the most likely conduction mechanism. One diode array will be stored under vacuum conditions and the other array will be exposed to atmospheric conditions. The influence of oxygen and humidity will be evaluated by logging the I(V) behavior on a daily or weekly basis for these two diode arrays (one being stored in vacuum when not located at the test stand.) Students accepted for this project must have a strong interest in microelectronic materials, devices and fabrication techniques. The mentors for this project will fabricate the diode arrays. With a sufficient number of interested EE415 students, this EE499 project could become an EE415/416 Design project.
VIII. ATP Modeling of the Northwest Transmission Network
Here the students will have to contact the electrical utilities of the NW, install ATP (EMTP) in their laptops, learn how to run ATP, and analyze simulation results.
Excellent for students interested in Power Engineering. ATP is one of the most useful tools in Power System Analysis. Students will learn how to use ATP and the Northwest Electrical Network.
IX. Analog Circuit for Ratio Measurements
Statement of Work
An analog circuit is needed to perform a ratio of two signals (R&S) in the frequency domain in the range (100Hz – 1MHz). This circuit could be used to measure the impedance of a network at a given frequency (Signal C) if Signal R was the applied voltage and Signal S was the applied current or any circuit needing a discrete FFT function performed. The Analog Devices AD734, four-quadrant multiplier, is a hardware component to consider performing this operation.
A little background on analog multiplier (mixer) operation may help scope the task a little more clearly and provide some insight into my concerns. The AD734, analog multiplier has the following inputs (X1, X2, Y1, Y2, and U), can perform the following transfer function:
W = (X1 – X2) * (Y1 – Y2) / U
We want to set X1 = ARcos(wt + fR) and X2 = 0, Y1 = AScos(wt + fS), Y2 = 0, and U = Accos(wt + fc).
Using standard math functions, Acos(a)*Bcos(b) = A*B*cos(a-b)/2 + A*B*cos(a+b)/2. So the multiplication of a reference frequency (C) by either the voltage or current signal using the X and Y inputs to the AD734 is straight forward and low pass filters could be used to eliminate the a+b frequency component. However, the desired effect is to form a ratio between the voltage and current signals. The introduction of the third signal causes two potential issues. The first issue is insuring that the circuit output will represent the desired quantity. This might initially be done by modeling and followed up experimentally. The second issue is what will happen when the voltage and current signal frequency content includes a broad range of frequencies. Of particular concern are intermodulation distortion effects (reference: Microwave Journal, January 2002, pp 20-40).
The ideal result would be that a single IC such as the AD734 would perform the desired function. If so, are there other components that could provide a similar performance at lower cost (including support components, buffers, decoupling, bias components, dividers, power consumption, bandwidth, power supplies needed, etc.). If using a single AD734 is not possible, design, modeling and testing of a multi-component circuit should be performed,
The above circuit segment (if successful) would perform the initial portion of a larger circuit segment that transforms the impedance at a given frequency into magnitude and phase. The rate at which the reference frequency is changed is slow (i.e. 10Hz) relative to the frequencies being used in the impedance measurement. Digitizing the impedance vector values and calculating magnitude and phase may be the easiest way to perform this last step. Texas Instrument makes a series of processors (MSP430Fxxxx) that may perform this function simply and inexpensively.
X. Video Functional Tester or Duplex Voice Coder
Video Functional
Tester
Verifying the visual output of mobile devices in the R&D lab is often very time-consuming, expensive, and inaccurate. Typically an operator is required to push buttons and subjectively verify that the output is “close enough” to the intended display. The “close enough” judgment can vary greatly between operators. These problems are particularly troublesome when testing high-resolution, multi-color displays that are popular on mobile devices.
This project would provide a means to automatically test the keypad and color display of a handheld device. The solution should provide a means to automatically control the keypad of a handheld device and a method to compare the displayed video to a captured known-correct video image. If there are differences between the displayed and captured video images, then the differences are to be highlighted and displayed to the operator of the test system or stored for later analysis.
Duplex Voice Coder
Digital mobile telephony systems send voice signals over the air in digitized, compressed formats. The compression and decompression of the audio signals are performed in algorithms known as voice coders (a.k.a., vocoders and codecs). Normally these algorithms are formally specified as part of the air interface standard for the wireless system.
This project would implement a mobile wireless device vocoder that takes a spoken or generated analog signal as input and generates voice coded data frames. The coded frames could then be looped back and decoded to produce an audio signal. The output of the encoder can be fed directly into the decoder or can also be stored in a file structure. Likewise, the input to the decoder can come directly from the encoder or can be coded audio frames sourced from a file.
The format of the data in the stored files shall be compatible with a chosen air interface message payload structure.
XI. Sigma Delta Analog-to-Digital Converter Circuit Design or Integrated Circuit Current Mirror Synthesis Tool
Project
1, Sigma Delta Analog-to-Digital Converter Circuit Design
Motivation –The increasingly dominant role of digital
design in system-on-a-chip applications elevates the importance of signal
conversion circuits (e.g. analog-to-digital converters) for analog designers
while also dictating analog circuit requirements. Even with CMOS logic,
million-gate integrated circuits, such as state-of-the art microprocessors,
require low voltage supplies to avoid excessive power dissipation. The Pentium
IV processor, for example, would dissipate 475 Watts if it used traditional 5 V
supplies. For system-on-a-chip applications, the low-voltage supplies make
analog design more challenging. They limit available circuit topologies (e.g. cascoding) and reduce noise margins (making fully
differential design mandatory). These factors make it important for a
mixed-signal ASIC design center to have a state-of-the-art low-voltage,
high-speed, analog-to-digital converter. Recent work has focused on SD
converters
because, they
offer a combination of high-resolution, low noise, and linearity. They also
minimize analog components leading to improved stability. A recent SD converter
achieved 14-bit accuracy at 4 MSPS while operating at only 1.8 V. The design
required careful clock distribution design, fully-differential signal path
design, and careful layout.
Summary – This project develops a low-voltage
high-speed precision SD analog-to-digital converter for use as a library cell
in the design of integrated circuits. The project ends before layout begins and
uses available models to avoid extra effort in setting up technology files in
an IC design environment. Although this project will not complete the layout of
the cell, the descriptions of the topology and design techniques that students
provide will help in its final design. Occasionally foundries provide free
fabrication runs. If a fabrication run and requested research funding is
available when the design is completed, the cell could be fabricated, tested,
documented, and enter the cell library.
Objectives – This project is intended to be a learning
tool to acquaint students with mixed-signal application-specific integrated
circuit design, team engineering disciplines, and open-ended project management
encountered in workplace engineering environments. Learning objectives for the
students include low-voltage circuit design techniques, high-speed clock and
analog design (possibly including delay-locked-loops), SD converter
architectures, integrated circuit design techniques, ADC specifications, and
project planning. The goal is to make available a low-voltage, high-speed,
precision SD converter library cell that could be used in system-on-a-chip
applications. This goal is likely to be too ambitious for the time available to
the students, however, and is expected to be completed by Boeing. A recommended
minimum set of objectives for the student project includes the following.
§ An overall
project plan
§ A description
demonstrating an understanding of how a SD converter works, its
limitations, and
its strengths.
§ A discussion of
the merits of circuit topology trade-offs that were considered with multiple
references to recent literature.
§ A description of
the chosen design topology and the rationale used to select it.
§ A block diagram
showing how the design has been partitioned into functional
components that
implement the converter.
§ Circuit diagrams
for each of the components.
§ A description of
low-voltage analog design techniques used, the design methods, and
equations used to
design each component.
§ Simulation
results providing performance information indicating that the individual
components
function as designed with the loading to be encountered when integrated
into the system.
(This would normally require technology files for an actual integrated
circuit design,
however, in order to avoid having to obtain non-disclosure agreements and
expensive
integrated circuit design tools and to avoid having to set up an IC process,
the
design can be
based on discrete CMOS transistor models)
§ A description of
system-level interconnect, power routing, grounding, and layout
considerations
needed to minimize noise coupling and signal timing problems.
§ A top-level
simulation showing how well the circuit is expected to perform. Note:
Mixed-signal simulations can be time-consuming if modeled at the
transistor-level. This is a typical problem encountered in large designs.
Careful selection of a mixture of
behavioral- and
transistor-level modeling avoids unreasonable simulation times.
§ A preliminary
top-level layout with functional blocks, inputs, outputs, and signal paths
identified. This
can be based on rough transistor size guesses. The actual sizes are not
as important as
the relative placement and signal flow.
§ A data sheet
with a list highlighting design features, a block diagram, and a performance
summary table based on simulation results. Be sure to include an indication of
the number of bits, sample rate, and total conversion time. Include as many of
the standard ADC parameters as possible. Noise simulation is not required but
be aware of the sources of noise in the circuit. Focus effort on the analog
design and more challenging aspects of the digital design rather than planning
complex digital interface features. Assume that a library of digital cells is
available with varying fan-out strengths so that none of the digital design
need be done at the transistor level. As time permits, look into layout
techniques and lay out critical elements of the circuit.
Skills Needed – Transistor-level analog circuit design,
digital logic design, and simulation capability are required. An awareness of integrated
circuit design techniques, some knowledge of low-voltage circuit techniques,
understanding of digital signal processing (z-domain analysis), knowledge of
high-speed design techniques, and analog/digital integrated circuit layout is
helpful but could be acquired as needed as the project progresses. The ideal
team would have an analog designer, a digital designer, an integrated circuit
layout designer (optional), and a system architect to pull all of these
elements together (usually this would be the team leader). This group would be
required to work closely together to plan the project, research currently
available literature, decide on an architecture, develop performance goals, and
functional requirements, and decide on and carry out specific design
assignments. Engineering communication skills are needed to keep team members
in synch, generate any required design review materials, and pull together a
final report. Coordination with a resident advisor will be required.
Project
2, Integrated Circuit Current Mirror Synthesis Tool
Motivation - Analog integrated circuit design is not yet
as mature as digital design where Very High Speed Integrated Circuit Hardware
Description Language (VHDL) code can be synthesized directly into a netlist. There are many degrees of freedom in analog design
and designers are often unwilling to compromise performance to minimize
development costs. Simply porting an IC design from one process to another can
cost over a million dollars. However, much progress has been made recently. For
example, NeoLinear provides a tool called NeoCircuit that optimizes parameter values of devices on an
integrated circuit using requirements, test benches, and circuit topology.
Then, after the design has been “sized”, it can be automatically laid out using
a tool called NeoCircuit and information about
matching, symmetry, and relative placement supplied by the designer. However,
even this tool-set is limited. It cannot select the topology and it cannot
optimize placement to minimize the effects of thermal gradients, mounting
stresses, and process gradients. The ASIC design industry is still a long way
from translating Analog HDL to netlists. Our group at
Boeing uses the NeoLinear tools combined with
in-house developed tools that automate design and layout of a selected set of
sub-circuits that are used repeatedly in IC design. Examples include resistor
and capacitor networks, current mirrors, and differential pairs. These circuits
are candidates for automated layout generation because they are relatively
simple and used universally. The resistor network design tool can be
demonstrated as an example.
Summary - Current mirrors are probably the most
utilized sub-circuit in IC design. They supply current to input, intermediate,
and output stages of op-amps and comparators. By generating an accurate,
temperature-compensated current source at one location in the IC and using
current mirrors, all components can be supplied with accurate reference
currents. Furthermore, reference currents can be routed over significant
distances in an IC with less noise pickup than can be achieved when routing
reference voltages. Currents can conveniently and accurately be multiplied in
current mirrors by simply paralleling transistors in the reflecting output
taps. The extensive use of current mirrors means that automation of their
design has the potential to contribute significantly to IC design efficiency.
Ideally, the requirements could be entered and a circuit design and layout will
be generated automatically. This has been achieved for resistor networks and
design quality has improved in the process. What formerly required an entire
week of effort can now be accomplished in 10 to 15 minutes. There are many
current source topologies for example the Widlar and
noted that once a
topology is selected, accuracy of the mirror depends on how good the layout is.
All of the transistors in a current mirror should be collocated and, if
possible, laid out with a common-centroid so that
thermal and process gradients have minimum effect on mismatch.
Circuit
available from Prof. Olsen
Figure 1. Bipolar Widlar, Wilson, and Cascoded
Current Mirrors
Objectives
– This project
is intended to be a learning tool to acquaint students with analog integrated
circuit design, team engineering disciplines, and open-ended project management
encountered in workplace engineering environments. Learning objectives for the
students include analog integrated circuit design and layout techniques,
automated tool algorithm development, and project planning. The goal would be
to make available a set of algorithms that can translate output impedance,
current tap weight, operating output voltage range, and source/sink
requirements into a circuit topology and optimized layout. However, this goal
is likely to be too ambitious for the time available. A recommended minimum set
of objectives would include the following.
· An
overall project plan
·
Survey current mirror topologies and recommend topologies that can be used with
various
supply
voltage ranges, output impedance, bandwidth, and output voltage swing
requirements.
Explain
how a current mirror works and discuss the limitations and strengths of each
topology.
·
Collect available models mapping device geometries and number of gate stripes
to
performance
parameters. To avoid having to obtain non-disclosure agreements from
foundries
and setting up foundry technology files, commonly available design rules can be
used. One possible source of this information is Harry Li’s book “CMOS Circuit
Design, Layout, and Simulation”, IEEE press, 1998, Appendix A. This reference
has models and layout rules. Another possible source of design rule information
is available at the MOSIS website: (http://www.mosis.com/Technical/Designrules/scmos/scmos-main.html)
· For
bulk NMOS and PMOS current mirrors, summarize all equations used to analyze
current mirror performance.
· List
process parameter inputs needed for the design equations and algorithms (e.g.
gate
oxide
thickness, mobility,...).
·
Determine performance envelopes for which circuits can be synthesized and how
they relate to the process parameters.
· Develop
algorithms needed to automatically select a topology and synthesize designs
from performance requirements, and when no topology can meet the requirements
provide an indication. Flow charts are acceptable. A BASIC, C, or C++
implementation of the topology selection algorithms with text-based input and
output is preferred.
·
Develop algorithms to synthesize layout geometries from performance inputs. A
small Visual Basic windows application is available and can be provided by the
project sponsor to demonstrate the process of converting tap weights into
common-centroid 1- and 2-D layout arrangements.
·
Estimate current matching performance in the presence of thermal gradients.
·
Start with an NMOS implementation, then do the same for PMOS, NPN, and PNP mirrors
as time permits. Use either bulk Si or Si-on-insulator with a P-substrate.
The objectives for the project are to develop a synthesis tool – not an analysis tool. Focus on the design algorithms rather than developing applications with extensive user interface capabilities.
Optionally
as time permits, include parasitics in equivalent
circuit models, develop algorithms for NPN and PNP transistors.
Skills
Needed – Analog
circuit design and simulation ability is required. Integrated circuit design
techniques, integrated circuit layout, and programming background are helpful
but can be obtained as needed as the project progresses. The ideal team would
have an analog designer, an integrated circuit layout designer, a programmer,
and a project manager. This group would be required to work closely together to
plan the project, research currently available literature, decide on the scope
of the effort, pull together algorithms based on the results of team member’s
work, and carry out specific design assignments. Engineering communication
skills are needed to keep team members in synch, generate any required design
review materials, and pull together a final report. Coordination with a
resident advisor will be required.
XII. Wireless LAN Interference
A. Problem
Several new classes of wireless Personal Area Network
(PAN) devices, designated by the IEEE as 802.15.3, are being developed as a
higher bandwidth, lower cost alternatives to existing 802.11b and 802.11a
wireless Local Area Networks (LAN).
B. REQUIREMENT
Connexion By Boeing desires to know if the new high rate 802.15.3[1]
devices operating as ad-hoc peers have the ability to disrupt either an
802.11b, or an 802.11a LAN, operating in an organized infrastructure mode. Additionally, if interference is possible, Connexion would like to know or understand the
circumstances, such as power levels and distance, at which the performance or
throughput of each device is either degraded, or ceases completely. This work should incorporate both the
standard[2]
and alternate[3] physical
layer devices. If additional time
permits, Connexion would also like to know if the
waveforms have any special propagation properties, such as, resistance to
multi-path interference from metal structures (e.g. aircraft cabin, rail car),
and the ability to either pass-through or be absorbed by various office
building interior structures, such as chairs and cubical walls.
XIII. Online Radio Frequency Characterization Of Semiconductor Devices And Mixed Signal Integrated Circuits
this
project aims at developing an online radio frequency device and mixed signal IC
characterization facility at the
- the instruments in the RF Device and mixed signal IC characterization laboratory (room eme B24). These include network analyzer (up to 13.5 GHz), Capacitance meter, dc semiconductor parameter analyzer, noise figure meter, spectrum analyzer, dc power supplies, to name a few.
- Agilent IC-CAP software which includes drivers for the above instruments to issue commands for making proper measurements by sweeping frequency or bias voltages, analysis or the resulting data, and extraction of SPICE model parameters for active and passive devices.
- National Instruments GPIB control cards to connect the instruments to a PC or network.
- National Instruments Lab View software to write the proper control sequence.
Each of the instruments has a GPIB port which allows
connecting all of them together using GPIB cables and assigning each instrument
a distinct ID similar to how SCSI hard drives are connected together in a PC.
One end of the cable is connected to a national instrument GBIP Card. There are two types of cards:
(a) One that fits into a PC motherboard PCI slot.
(b) One that connects directly to the network with a distinct network ID.
Both types of cards will be used in this project. During the first phase, a PCI card will used and both IC-CAP and Lab View software will be installed on a PC. This allows addressing issues related to interface between the instruments and IC-CAP software. The group will be provided with IC chips to make the measurements. The IC chips or dies will be placed on probe station chuck and connected to the instrument through RF or DC probes and cables. During the second phase a national instrument card will connect the instruments to the network. The end goal of this phase will be to allow anyone on the EECS network to use IC-CAP to make measurements using the instruments in EME B24 on chips that are already placed on the probe station. Such test facility allows making measurements remotely and in an industrial environment (INTEL, Micron, HP, etc.) allows making measurements on full size wafers using special types of probes.
XIV. Bi-directional Computer Modem
Based on DSP Demonstration Boards
Project Description
Implement modems to transfer bi-directional data between two personal computers. Maximize data rate and minimize errors of signals sent through the channel simulator provided. To minimize constriction problems it is intended that the team adapt DSP demonstration modules such as the TI TMS320C5x Starter Kit ($400) to build the modems.
Tasks Required:
Characterize the telephone channel simulator. Design and fabricate the analog circuitry required to adapt the DSP module’s I/O to the telephone line simulator. Analyze the limitations imposed by the telephone line and choose a modulation method for the physical layer. Analyze and choose coding and error correction techniques. Write DSP software to implement the desired system. Write any PC software necessary to control and operate the DSP system via the data interface.
References:
Electronic Engineer’s Handbook second edition, Donald F. Fink editor, pp 22-20 to 22-25
Reference Data for Radio Engineers. Chapter two of the 5th or 6th editions.
Discussion:
This project is an opportunity to apply DSP to telecommunications problems. It is intended to provide a challenging and entertaining capstone design project for a team of students with skills in DSP, software, and analog design. Normally, designing a DSP based system requires a great deal of work just to get started. The ECB must be designed and fabricated before DSP software work can even begin. The use of inexpensive DSP hardware modules focuses the project mostly on writing and debugging DSP software.
Building a modem to an existing standard is beyond the scope and off the point of a university course. The effort to research and understand complex telecommunications standards would not serve to teach or illustrate communications principles. Designing one’s own system of modulation, coding, and error correcting does this much better.
A half-duplex (only one end transmits at a time) protocol instead of a full-duplex system (both ends transmit simultaneously) is acceptable. This simplifies both the hardware and the software.
The baud rate was deliberately not specified: it is to be selected by the team. This allows some flexibility to the project’s scope. If a low data rate of only a few hundred baud is selected, FSK signaling can be used in a simple implementation. If rates above a k-baud or two are selected, more complicated modulation schemes are required. If a state of the art rate is selected (>20 k-baud) the link will require adaptive equalization combined with complex modulation, error correction, and coding techniques.
The author recommends a modest 1 or 2 k-baud rate unless someone with extensive telecommunications skills is available to work on the project.
Real telephone systems can exhibit substantial (10’s of mS) delays between transmitting a signal and receiving an acknowledgment from the other end. Each modem must adapt to the frequency sent by the other since frequency references have small errors. There also may be up to a 1 Hz frequency offset caused by the telephone system itself. It is important to remember that all communications and/or synchronization signals must be passed through the channel simulator. The modems shall not rely on any other frequency or phase reference such as the power line.
The data signal from the modems shall be AC coupled to the phone line (see below). It is permissible but not necessary to provide an off-hook switched DC connection and dialing tones. Adding these features will substantially increase the scope of the project.
Channel Simulator:
The simple channel simulator provided models the frequency band limiting, insertion loss, and amplitude limitations of a telephone channel. It does not emulate the envelope delay of a poor telephone link nor does it provide the real telephone interface’s signaling functions or its low level noise floor. Its intent is to provide a response similar to a long distance telephone channel, not simulate a phone interface.
When working with telephone lines, source impedance is very important. Too low or high of a source impedance can cause the frequency response to droop or peak. The channel simulator must be driven from a balanced 600 ohm source to obtain the correct results. Signals into a telephone interface must not exceed 0 dBm (dB with respect to 1 mW). However, when transmitting signaling tones (i.e. data), only –10 dBm may be transmitted. The channel simulator will clip signals above about 0 dBm input.
Telephone systems use a 48 VDC voltage to provide current to operate ordinary telephones (biasing current for carbon microphones) and to provide means to send signals to the central offices (off hook, make and break dialing). Off the shelf modem equipment manipulates the DC signaling to alert the central office of a call attempt, etc. All other functions are AC coupled.
Fig 1.
Telephone Channel Simulator
a) Amplitude Function: Similar to a long distance telephone channel
Impedance: 600 ohms, balanced
Frequency Response (3dB): ~600 Hz to ~2700 Hz
Mid-band Insertion Loss: ~5 dB
Maximum Amplitude: 0 dBm (1 mW)
Maximum Signaling Tone Amplitude: -10 dBm
XV. Maze Following Robot, FPGA Based Computer System or Motion Tracking Camera System
Maze-following Robot
This project involves the design and implementation of a robot that can learn to navigate a maze. The robot drive train and electronics will be based on the Digibot developed by an earlier senior project team. In operation, the robot will drive into the maze until a wall is encountered, and then it will turn left or right and proceed until a wall is encountered, etc. The robot must map its course, retracing its route if necessary, until the maze is solved. Once solved, the robot should be able to navigate the maze from start to finish with no wrong turns. The major additions/modifications to the Digibot include are chassis redesign, sensors, and control and mapping algorithms. Deliverables will include robot schematics, a theory of operation/user guide, and source code for the robots processors.
FPGA-based computer
system
This project involves the creation of a computer system in a single FPGA based on the Xilinx MicroBlaze RISC processor core (or, if feasible, on a 6811 core being implemented now by another senior design team). The computer system will be use hardware from the Digilent Company. System components, all designed in VHDL, will include a processor system with an external ROM and RAM controller, a keyboard interface, a display system, and a removable media controller. The computer may use an off-the-shelf operating system, but we will also explore the development of a new, custom operating system. The project will also involve the creation of at least one application program written in C. Deliverables will include VHDL source code for system components, and the C source for application programs.
Motion-tracking
camera system
This project involves the design and implementation of a camera system that can track a moving object. The camera will be mounted on a tilt and swivel mechanism that can be controlled by a PC. The camera system must track a token (like a red dot or LED) attached to a moving object, and then keep that token centered in the image as the object moves. The test case will be tracking a model rocket as it launches. The camera system will use a low-cost VGA imager mounted on a custom tilt and swivel head, with tethered video signal transmission to a PC located close by. The major design challenges include video processing to track the token, and control electronics and algorithms to move the camera head. Deliverables include the C source code for the image processor and camera positioning software, and schematics for the camera head system.
I. Performance Evaluation of PC’s
Overview:
PC’s have multiple bottlenecks to data throughput. The goal of is this project is to overcome some of these bottlenecks and to document the results.
Desired Outcome:
· Identify a set of hardware and software that achieves the highest data throughput from one PC to another.
· Produce graphs that show the performance levels on a PC running software utilities on Windows 2000 and Linux.
· Develop a performance model for each of the key elements in the system.
Tasks:
1. Set up base PC rack system with Gigabit LAN. Measure LAN throughput and disk throughput.
2. Develop a set of performance experiments with the guidance of an HP mentor.
3. Develop a schedule for development and then track it through weekly phone conference calls.
4. Write a report that summarizes the results and makes a final recommendation.
Possible Areas to Explore:
· Data throughput using various LAN types. Also explore throughput of various LAN protocols.
· Effects of using RAID 5 configured disk arrays on performance. Compare to performance of RAID 0 striped disks.
· Explore effects of the Windows and Linux OS’s on a set of test applications.
HP Support Proposal:
· Supply a small rack of up to 4 HP servers.
· Servers would be on long-term loan to the college for future use by the college.
· Supply an HP mentor to work with the WSU team.