BSEE, University of Portland, 2002

MSEE, Washington State University, 2004

Ph.D., Washington State University, 2006

Reconfigurable Hardware, VLSI Design, and DSP.

M. Myjak and J. G. Delgado-Frias, “Medium-Grain Cells for Reconfigurable DSP Hardware,” IEEE Transactions on Circuits and Systems, I: Fundamental Theory and Applications, vol. 54, no 6, pp. 1255-1265, June 2007.

M. Myjak and J. G. Delgado-Frias, “A Two-Level Reconfigurable Cell Array for Digital Signal Processing,” The Microelectronic Engineering Journal, vol. 84, no. 2, pp. 244-253, February 2007.

M. J. Myjak, J. G. Delgado-Frias, and S. K. Jeon, “An Energy-Efficient Differential Flip-Flop for Deeply Pipelined Systems,” 49th IEEE Int. Midwest Symposium on Circuits and Systems, August 6-9, 2006.

M. J. Myjak, J. K. Larson, and J. G. Delgado-Frias, “Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture,” International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, June 26-29, 2006.

M. J. Myjak and J. G. Delgado-Frias, “Superpipelined reconfigurable hardware for DSP,” 2006 IEEE International Symposium on Circuits and Systems, pp. 3670-3673, Kos, Greece, May 21-24, 2006.

M. J. Myjak, and J. G. Delgado-Frias, “A Bit-Serial Cell for Reconfigurable DSP Hardware,” 48th IEEE Int. Midwest Symposium on Circuits and Systems, Aug. 2005.

M. J. Myjak, and J. G. Delgado-Frias, “A Symmetric Differential Clock Generator for Bit-Serial Hardware,” The 2005 International Conference on Computer Design, pp. 159-164, Las Vegas, June 2005.

D. R. Blum, M. J. Myjak, and J. G. Delgado-Frias, “Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS,” The 2005 International Conference on Computer Design, pp. 28-34, Las Vegas, June 2005.

M. Myjak, D. Blum, and J. Delgado-Frias, Enhanced fault-tolerant CMOS memory elements, in Proc. 2004 IEEE International Midwest Symposium on Circuits and Systems, Hiroshima, Japan, Jul. 2004.

M. Myjak, F. Anderson, and J. Delgado-Frias, H-tree interconnection structure for reconfigurable DSP hardware, in Proc. 2004 International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, NV, pp. 170-176, Jun. 2004.

M. Myjak and J. Delgado-Frias, Pipelined multipliers for reconfigurable hardware, in Proc. 2004 Reconfigurable Architectures Workshop, Santa Fé, NM, pp. 150-156, Apr. 2004.

M. J. Myjak and J. G. Delgado-Frias, "A Two-Level Reconfigurable Architecture for Digital Signal Processing," The 2003 International Conference on VLSI (VLSI'03), Las Vegas, Nevada, June 23-26, 2003.  (PDF)

J. G. Delgado-Frias, M. J. Myjak, F. L. Anderson, and D. R. Blum, "A Medium-Grain Reconfigurable Cell Array for DSP Applications," IASTED International Conference on Circuits, Signal and Systems (CSS 2003), Cancun, Mexico, pp. 231-236, May 2003. (PDF)